1. Field of the Invention
The present invention relates to a nonvolatile semiconductor storage device, such as a flash memory, etc., and a method for manufacturing the same.
2. Description of the Related Art
Flash memories are known as one type of nonvolatile memory. Among flash memories, there are those in which element isolation is achieved by a LOCOS (local oxidation of silicon) structure and those in which element isolation is achieved by an STI (shallow trench isolation) structure. In comparison to a LOCOS structure, an STI structure has an advantage of enabling reduction of memory cell size.
FIG. 4 is a schematic sectional view of a flash memory having an STI structure.
The flash memory 101 includes a silicon substrate 102. A plurality of trenches 103 are formed in parallel at fixed intervals in the silicon substrate 102.
An embedded body 104, made of silicon oxide (SiO2) is embedded in each trench 103. The embedded body 104 protrudes from a top surface of the silicon substrate 102, and a side surface of the protruding portion is a flat surface orthogonal to the top surface of the silicon substrate 102. Also, an upper surface of the embedded body 104 is a flat surface orthogonal to the side surface and parallel to the top surface of the silicon substrate 102.
A tunnel oxide film 105 is formed on the top surface of the silicon substrate 102.
At a side of the embedded body 104 in a direction orthogonal to a direction of extension of the trench 103, a floating gate 108, made of a first polysilicon layer 106 and a second polysilicon layer 107, is formed on the tunnel oxide film 105. The floating gate 108 has a predetermined width in the direction of extension of the trench 103.
The first polysilicon layer 106 and the second polysilicon layer 107 are laminated in that order on the tunnel oxide film 105. An interface between the first polysilicon layer 106 and the second polysilicon layer 107 is positioned more toward the silicon substrate 102 side than the upper surface of the embedded body 104. A side surface of the first polysilicon layer 106 and a side surface of a bottom portion of the second polysilicon layer 107 are thus in contact with the side surface of the embedded body 104. The side surface of the second polysilicon layer 107 is a flat surface orthogonal to the upper surface of the embedded body 104. An upper surface of the second polysilicon layer 107 is a flat surface parallel to the top surface of the silicon substrate 102.
An insulating film 109 having an ONO (oxide-nitride-oxide) structure is formed on the upper surface and the side surface, in the direction orthogonal to the direction of extension of the trench 103, of the second polysilicon layer 107. The insulating film 109 is also formed on the embedded body 104 and extends continuously and rectilinearly via tops of the plurality of floating gates 108 that are aligned in the direction of extension of the trenches 103.
A control gate 110, made of polysilicon, is formed on the insulating film 109. The control gate 110 is formed not only above the floating gate 108 but also to the side thereof.
In the flash memory 101 shown in FIG. 4, not only the upper surface of the floating gate 108 but also the side surface of the floating gate 108 opposes the control gate 110 via the insulating film 109, and enlargement of an area of opposition of the floating gate 108 and the control gate 110 is thereby achieved. By enlargement of the area of opposition of the floating gate 108 and the control gate 110, a capacitance CONO between the floating gate 108 and the control gate 110 is increased, and a coupling ratio CONO/(CONO+CTOX), which is a ratio of the capacitance CONO with respect to a sum of the capacitance CONO and a capacitance CTOX between the silicon substrate 102 and the floating gate 108, is made large. The larger the coupling ratio becomes, the more an operation margin (operation stability) of the flash memory 101 is improved.
However, further increase of the coupling ratio is being demanded recently, and for this purpose, an innovation is required in the structure of the memory cell.